![]() Catapult C has 3 types of simulation using the original C/C++ testbench: Cycle-based, RTL-based, and Gate-Level based. Catapult has a graphic user interface with a visual view of the hardware circuit it is scheduling, as well as the clock reference between the C code and the Verilog RTL code. ĭesigners do iterations with CatC to pick their preferred micro architecture for specified performance and area constraints. Ĭatapult C supports both algorithmic and control logic synthesis. The C/C++ language support includes pointers, classes, templates, template specialization and operator overloading, which facilitate design reuse methodology over RTL code. In September 2015, Mentor Graphics acquired Calypto Design Systems, thus reacquiring Catapult C.ĬatapultC synthesizes ANSI C/C++ without proprietary extensions. In August 2011, Catapult C was acquired by Calypto Design Systems. Existing synthesizable descriptions can be converted to TLMs. Abstract TLM models are converted to pin-accurate, protocol-specific, SystemC models, and from there, synthesized to RTL code. In May 2011, Mentor announced that Catapult C supported TLM synthesis. ![]() In January 2010, Mentor announced the ability for Catapult C to take direct SystemC input, including both cycle-based and transaction level (TLM) support. In June 2009, Mentor announced that it enhanced Catapult C with the ability to synthesize control logic, create power-optimized RTL netlists, with automatic multi-level clock gating, and an automated verification flow to enable a debug of the RTL against the original C++ input. The flow is compatible with the TLM-2.0 standard from the Open SystemC Initiative (OSCI). In this process, the untimed ANSI C++ input to Catapult is encapsulated in a TLM wrapper timing information is extracted from the synthesis results and back-annotated in the resulting model. In January 2009, Mentor announced an integration between Catapult C and its Vista SystemC design and simulation environment to automatically generate transaction-level models (TLM). ![]() Catapult SL automatically inserts appropriate inter-block channels and memory buffers to assemble the sub-system. ![]() Catapult SL could coordinate the partitioning of sequential C operations into multiple blocks within the subsystem, including partitioning into multiple clock domains. In 2006, Mentor announced Catapult SL (System Level) for automatically creating signal processing subsystems. Mentor also introduced interface synthesis to map the data transfer implied by passing of C++ function arguments to hardware interfaces such as wires, registers, handshaked registers, memories, buses or more complex user-defined interfaces. In 2005, Mentor announced extensions to Catapult C to automatically create SystemC transaction-level models and wrappers, for simulation of the design in verification environments supporting SystemC. Mentor also announced a Catapult C Library Builder for ASIC Designers to collect detailed characterization data. Users specified constraints for timing and area, and provided a clock period and destination technology. Catapult C's main functionality was generating RTL ( VHDL and Verilog) targeted to ASICs and FPGAs. In 2004, Mentor Graphics formally announced its Catapult C high level synthesis product offering hierarchical design support for synthesizing pipelined, multi-block subsystems from untimed ANSI C/C++ descriptions.
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